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opa692 sbos236c C march 2002 C revised january 2003 www.ti.com description the opa692 provides an easy to use, broadband fixed gain video buffer amplifier. depending on the external connec- tions, the internal resistor network may be used to provide either a fixed gain of +2 video buffer or a gain of +1 or C1 voltage buffer. operating on a very low 5.1ma supply cur- rent, the opa692 offers a slew rate and output power normally associated with a much higher supply current. a new output stage architecture delivers high output current with minimal headroom and crossover distortion. this gives exceptional single-supply operation. using a single +5v supply, the opa692 can deliver a 1v to 4v output swing with over 120ma drive current and > 200mhz bandwidth. this combination of features makes the opa692 an ideal rgb line driver or single-supply analog-to-digital converter (adc) input driver. the low 5.1ma supply current for the opa692 is precisely trimmed at +25 c. this trim, along with low drift over tem- perature, ensures a lower maximum supply current than competing products that report only a room temperature nominal supply current. system power may be further re- duced by using the optional disable control pin. leaving this disable pin open, or holding it high, gives normal operation. if pulled low, the opa692 supply current drops to less than 150 a while the i/o pins go into a high-impedance state. features flexible supply range: +5v to +12v single supply 2.5v to 6v dual supplies internally fixed gain: +2 or 1 high bandwidth (g = +2): 225mhz low supply current: 5.1ma low disabled current: 150 a high output current: 190ma output voltage swing: 4.0v sot23-6 available copyright ? 2002-2003, texas instruments incorporated wideband, fixed gain video buffer amplifier with disable please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. applications broadband video line drivers multiple line video da portable instruments adc buffers active filters o p a 6 9 2 o p a 6 9 2 opa692 related products singles duals triples voltage-feedback opa690 opa2690 opa3690 current-feedback opa691 opa2691 opa3691 fixed gain opa682 opa2682 opa3692 video out 75 ? 75 ? rg-59 75 ? 75 ? rg-59 75 ? 75 ? rg-59 75 ? 75 ? rg-59 75 ? 1 2 3 4 8 7 6 5 dis opa692 so-8 g = +2 +5v C 5v video in production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 225mhz, 4-output component video da
opa692 2 sbos236c www.ti.com specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity OPA692ID so-8 surface-mount d C 40 c to +85 c opa692 OPA692ID rails, 100 """"" OPA692IDr tape and reel, 2500 OPA692IDbv sot23-6 dbv C 40 c to +85 c oagi OPA692IDbvt tape and reel, 250 """"" OPA692IDbvr tape and reel, 3000 notes: (1) for the most current specifications and package information, refer to our web site at www.ti.com. absolute maximum ratings (1) power supply ............................................................................... 6.5v dc internal power dissipation (2) ............................ see thermal information differential input voltage (3) ............................................................... 1.2v input voltage range ............................................................................ v s storage temperature range: d, dvb ........................... C 40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c esd resistance: hbm ........................................................................ 2kv mm ........................................................................ 200v notes: (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) packages must be derated based on specified ja . maximum t j must be observed. (3) noninverting input to internal inverting node. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. pin configuration top view so top view sot package/ordering information 1 2 3 4 8 7 6 5 dis +v s output nc r f 402 ? r g 402 ? nc C in +in C v s nc: no connection 1 2 3 6 5 4 output C v s +in +v s dis C in r f 402 ? r g 402 ? 123 654 oagi pin orientation/package marking
opa692 3 sbos236c www.ti.com electrical characteristics: v s = 5v boldface limits are tested at +25 c. g = +2 ( C in grounded) and r l = 100 ? (see figure 1 for ac performance only), unless otherwise noted. OPA692ID, idbv typ min/max over temperature 0 c to C 40 c to min/ test parameter conditions +25 c +25 c (1) 70 c +85 c units max level (2 ) ac performance (see figure 1) small-signal bandwidth (v o < 0.5vp-p) g = +1 280 mhz typ c g = +2 225 185 180 170 mhz min b g = C 1 220 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o < 0.5vp-p 120 40 35 30 mhz min b peaking at a gain of +1 v o < 0.5vp-p 0.2 1 1.5 2 db max b large-signal bandwidth g = +2, v o = 5vp-p 220 mhz typ c slew rate g = +2, 4v step 2000 1400 1375 1350 v/ sminb rise-and-fall time g = +2, v o = 0.5v step 1.6 ns typ c g = +2, v o = 5v step 1.9 ns typ c settling time to 0.02% g = +2, v o = 2v step 12 ns typ c 0.1% g = +2, v o = 2v step 8 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd-harmonic r l = 100 ? C 69 C 62 C 59 C 57 dbc max b r l 500 ? C 79 C 70 C 67 C 65 dbc max b 3rd-harmonic r l = 100 ? C 76 C 72 C 70 C 68 dbc max b r l 500 ? C 94 C 87 C 82 C 78 dbc max b input voltage noise f > 1mhz 1.7 2.5 2.9 3.1 nv/ hz max b noninverting input current noise f > 1mhz 12 14 15 15 pa/ hz max b inverting input current noise f > 1mhz 15 17 18 19 pa/ hz max b differential gain ntsc, r l = 150 ? 0.07 % typ c ntsc, r l = 37.5 ? 0.17 % typ c differential phase ntsc, r l = 150 ? 0.02 deg typ c ntsc, r l = 37.5 ? 0.07 deg typ c dc performance (3) gain error g = +1 0.2 % typ c g = +2 0.3 1.5 1.6 1.7 % max a g = C 1 0.2 1.5 1.6 1.7 % max b internal r f and r g maximum 402 457 462 464 ? max a minimum 402 347 342 340 ? min a average drift 0.13 0.13 0.13 %/c max b input offset voltage v cm = 0v 0.5 2.5 3.2 3.9 mv max a average offset voltage drift v cm = 0v 12 20 v/ cmax b noninverting input bias current v cm = 0v +15 +35 +43 +45 amaxa average noninverting input bias current drift v cm = 0v C 300 C 300 na/ cmax b inverting input bias current v cm = 0v 5 25 30 40 amaxa average inverting input bias current drift v cm = 0v 90 200 na cmaxb input common-mode input range 3.5 3.4 3.3 3.2 v min b noninverting input impedance 100 || 2 k ? || pf typ c output voltage output swing no load 4.0 3.8 3.7 3.6 v min a 100 ? load 3.9 3.7 3.6 3.3 v min a current output, sourcing +190 +160 +140 +100 ma min a sinking C 190 C 160 C 140 C 100 ma min a short-circuit current v o = 0 250 ma typ c closed-loop output impedance g = +2, f = 100khz 0.12 ? typ c notes: (1) junction temperature = ambient temperature for low temperature limit and +25 c specifications. junction temperature = ambient temperature +10 c at high temperature limit specifications. (2) test levels: (a) 100% tested at +25 c. over-temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (3) current is considered positive out-of-node. v cm is the input common-mode voltage.
opa692 4 sbos236c www.ti.com electrical characteristics: v s = 5v (cont.) boldface limits are tested at +25 c. g = +2 ( C in grounded) and r l = 100 ? (see figure 1 for ac performance only), unless otherwise noted. OPA692ID, idbv typ min/max over temperature 0 c to C 40 c to min/ test parameter conditions +25 c +25 c (1) 70 c +85 c units max level (2 ) disable/power down ( dis pin) power-down supply current (+v s )v dis = 0 C 150 C 300 C 350 C 400 amaxa disable time v in = +1v dc 1 s typ c enable time v in = +1v dc 25 ns typ c off isolation g = +2, 5mhz 70 db typ c output capacitance in disable 4 pf typ c turn-on glitch g = +2, r l = 150 ? 50 mv typ c turn-off glitch g = +2, r l = 150 ? 20 mv typ c enable voltage 3.3 3.5 3.6 3.7 v min a disable voltage 1.8 1.7 1.6 1.5 v max a control pin input bias current v dis = 0 75 130 150 160 amaxa power supply specified operating voltage 5 v typ c maximum operating voltage range 6 6 6vmaxa maximum quiescent current v s = 5v 5.1 5.3 5.5 5.8 ma max a minimum quiescent current v s = 5v 5.1 4.9 4.5 4.25 ma min a power-supply rejection ratio ( C psrr) input referred 58 52 50 49 db min a temperature range specification: d, dbv C 40 to +85 c typ c thermal resistance, ja dso-8 125 c/w typ c dbv sot23-6 150 c/w typ c notes: (1) junction temperature = ambient temperature for low temperature limit and +25 c specifications. junction temperature = ambient temperature +10 c at high temperature limit specifications. (2) test levels: (a) 100% tested at +25 c. over-temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (3) current is considered positive out-of-node. v cm is the input common-mode voltage.
opa692 5 sbos236c www.ti.com electrical characteristics: v s = +5v boldface limits are tested at +25 c. g = +2 ( C in grounded though 0.1 f) and r l = 100 ? to v s /2 (see figure 2 for ac performance only), unless otherwise noted. OPA692ID, idbv typ min/max over temperature 0 c to C 40 c to min/ test parameter conditions +25 c +25 c (1) 70 c +85 c units max level (2 ) ac performance (see figure 2) small-signal bandwidth (v o < 0.5vp-p) g = +1 240 mhz typ c g = +2 190 168 160 140 mhz min b g = C 1 195 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o < 0.5vp-p 90 40 30 25 mhz min b peaking at a gain of +1 v o < 0.5vp-p 0.2 1 2.5 3 db max b large-signal bandwidth g = +2, v o = 2vp-p 210 mhz typ c slew rate g = +2, 2v step 830 600 575 550 v/ sminb rise-and-fall time g = +2, v o = 0.5v step 2.0 ns typ c g = +2, v o = 2v step 2.3 ns typ c settling time to 0.02% g = +2, v o = 2v step 14 ns typ c 0.1% g = +2, v o = 2v step 10 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd-harmonic r l = 100 ? to v s /2 C 66 C 58 C 57 C 56 dbc max b r l 500 ? to v s /2 C 73 C 65 C 63 C 62 dbc max b 3rd-harmonic r l = 100 ? to v s /2 C 72 C 68 C 67 C 65 dbc max b r l 500 ? to v s /2 C 77 C 72 C 70 C 69 dbc max b input voltage noise f > 1mhz 1.7 2.5 2.9 3.1 nv/ hz max b noninverting input current noise f > 1mhz 12 14 15 15 pa/ hz max b inverting input current noise f > 1mhz 15 17 18 19 pa/ hz max b dc performance (3) gain error g = +1 0.2 % typ c g = +2 0.3 1.5 1.6 1.7 % max a g = C 1 0.2 1.5 1.6 1.7 % max b internal r f and r g maximum 402 457 462 464 ? max b minimum 402 347 342 340 ? min b average drift 0.13 0.13 0.13 %/c max b input offset voltage v cm = 2.5v 0.5 3 3.6 4.3 mv max a average offset voltage drift v cm = 2.5v 12 20 v/ cmax b noninverting input bias current v cm = 2.5v +20 +40 +46 +56 amaxa average noninverting input bias current drift v cm = 2.5v C 250 C 250 na/ cmax b inverting input bias current v cm = 2.5v 5 25 30 40 amaxa average inverting input bias current drift v cm = 2.5v 112 200 na cmaxb input least positive input voltage 1.5 1.6 1.7 1.8 v max b most positive input voltage 3.5 3.4 3.3 3.2 v min b noninverting input impedance 100 || 2 k ? || pf typ c output most positive output voltage no load 4.0 3.8 3.7 3.5 v min a r l = 100 ? 3.9 3.7 3.6 3.4 v min a least positive output voltage no load 1.0 1.2 1.3 1.5 v max a r l = 100 ? 1.1 1.3 1.4 1.6 v max a current output, sourcing +160 +120 +100 +80 ma min a sinking C 160 C 120 C 100 C 80 ma min a short-circuit current v o = v s /2 250 ma typ c output impedance g = +2, f = 100khz 0.12 ? typ c notes: (1) junction temperature = ambient temperature for low temperature limit and +25 c specifications. junction temperature = ambient temperature +10 c at high temperature limit specifications. (2) test levels: (a) 100% tested at +25 c. over-temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (3) current is considered positive out-of-node. v cm is the input common-mode voltage.
opa692 6 sbos236c www.ti.com electrical characteristics: v s = +5v (cont.) boldface limits are tested at +25 c. g = +2 ( C in grounded though 0.1 f) and r l = 100 ? to v s /2 (see figure 2 for ac performance only), unless otherwise noted. OPA692ID, idbv typ min/max over temperature 0 c to C 40 c to min/ test parameter conditions +25 c (1) +25 c70 c +85 c units max level (2 ) disable/power down ( dis pin) power-down supply current (+v s )v dis = 0 C 150 C 300 C 350 C 400 a typ c off isolation g = +2, 5mhz 65 db typ c output capacitance in disable 4 pf typ c turn-on glitch g = +2, r l = 150 ? , v in = 2.5v 50 mv typ b turn-off glitch g = +2, r l = 150 ? , v in = 2.5v 20 mv typ b enable voltage 3.3 3.5 3.6 3.7 v min b disable voltage 1.8 1.7 1.6 1.5 v max b control pin input bias current ( dis )v dis = 0 75 130 150 160 a typ c power supply specified single-supply operating voltage 5 v typ c maximum single-supply operating voltage 12 12 12 v max a maximum quiescent current v s = +5v 4.5 4.8 5.0 5.2 ma max a minimum quiescent current v s = +5v 4.5 4.1 3.8 3.7 ma min a power-supply rejection ratio (+psrr) input referred 55 db typ c temperature range specification: d, dbv C 40 to +85 c typ c thermal resistance, ja dso-8 125 c/w typ c dbv sot23-6 150 c/w typ c notes: (1) junction temperature = ambient temperature for low temperature limit and +25 c specifications. junction temperature = ambient temperature +10 c at high temperature limit specifications. (2) test levels: (a) 100% tested at +25 c. over-temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (3) current is considered positive out-of-node. v cm is the input common-mode voltage.
opa692 7 sbos236c www.ti.com typical characteristics: v s = 5v t a = +25 c, g = +2, and r l = 100 ? (see figure 1 for dc performance only), unless otherwise noted. 7 6 5 4 3 2 1 0 frequency (25mhz/div) 0 250mhz 125mhz large-signal frequency response gain (1db/div) v o = 1vp-p v o = 2vp-p v o = 7vp-p v o = 4vp-p 400 300 200 100 0 C 100 C 200 C 300 C 400 small-signal pulse response time (5ns/div) output voltage (100mv/div) v o = 0.5vp-p g = +2 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 number of 150 ? loads 1234 composite video dg/dp dp dp dg dg dg/dp (%/ ) opa692 video in video loads C 5v +5v dis optional 1.3k ? pull-down no pull-down with 1.3k ? pull-down 1 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 frequency (50mhz/div) 0 500mhz 250mhz small-signal frequency response normalized gain (1db/div) g = +2 g = +1 g = C 1 disabled feedthrough vs frequency C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 C 95 frequency (mhz) 1 0.5 10 100 feedthrough (5db/div) v dis = 0 reverse forward 4 3 2 1 0 C 1 C 2 C 3 C 4 large-signal pulse response time (5ns/div) output voltage (1v/div) v o = 5vp-p g = +2
opa692 8 sbos236c www.ti.com typical characteristics: v s = 5v (cont.) t a = +25 c, g = +2, and r l = 100 ? (see figure 1 for dc performance only), unless otherwise noted. C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 supply voltage ( v s ) 2 2.5 3 3.5 4 4.5 5 5.5 6 5mhz harmonic distortion vs supply voltage harmonic distortion (dbc) v o = 2vp-p r l = 100 ? f = 5mhz 2nd-harmonic 3rd-harmonic C 60 C 65 C 70 C 75 C 80 C 85 C 90 C 95 C 100 C 105 C 110 load resistance ( ? ) 100 1000 harmonic distortion vs load resistance harmonic distortion (dbc) v o = 2vp-p f = 5mhz 2nd-harmonic 3rd-harmonic C 65 C 70 C 75 C 80 C 85 output voltage swing (vp-p) 0.1 1 5 harmonic distortion vs output voltage harmonic distortion (dbc) r l = 100 ? f = 5mhz 2nd-harmonic 3rd-harmonic C 50 C 60 C 70 C 80 C 90 C 100 harmonic distortion vs frequency (g = +2) frequency (mhz) 0.1 1 10 20 harmonic distortion (dbc) dbc = db below carrier v o = 2vp-p r l = 100 ? 3rd-harmonic 2nd-harmonic C 50 C 60 C 70 C 80 C 90 C 100 harmonic distortion vs frequency (g = C 1) frequency (mhz) 0.1 1 10 20 harmonic distortion (dbc) dbc = db below carrier v o = 2vp-p r l = 100 ? 3rd-harmonic 2nd-harmonic harmonic distortion vs frequency (g = +1) frequency (mhz) 0.1 1 10 20 harmonic distortion (dbc) C 50 C 60 C 70 C 80 C 90 C 100 dbc = db below carrier v o = 2vp-p r l = 100 ? 2nd-harmonic 3rd-harmonic
opa692 9 sbos236c www.ti.com typical characteristics: v s = 5v (cont.) t a = +25 c, g = +2, and r l = 100 ? (see figure 1 for dc performance only), unless otherwise noted. 65 60 55 50 45 40 35 30 25 20 frequency (hz) 1k 10k 100k 1m 10m 100m psrr vs frequency power-supply rejection ratio (db) +psrr C psrr 60 50 40 30 20 10 0 capacitive load (pf) 1 10 100 1k recommended r s vs capacitive load r s ( ? ) 100 10 1 input voltage and current noise density frequency (hz) 100 1k 10k 100k 1m 10m current noise (pa/ hz) voltage noise (nv/ hz) noninverting current noise (12pa/ hz) inverting input current noise (15pa/ hz) voltage noise (1.7nv/ hz) C 30 C 40 C 50 C 60 C 70 C 80 C 90 2-tone, 3rd-order intermodulation spurious single-tone load power (dbm) C 8 C 6 C 4 C 20246810 3rd-order spurious level (dbc) dbc = db below carriers 50mhz 20mhz 10mhz load power at matched 50 ? load 9 6 3 0 C 3 C 6 C 9 frequency (25mhz/div) 0 250mhz 125mhz frequency response vs capacitive load normalized gain to capacitive load (db) opa692 r s v in v o c l 1k ? 402 ? 402 ? 1k ? is optional. c l = 10pf c l = 22pf c l = 47pf c l = 100pf 10 8 6 4 2 0 250 200 150 100 50 0 supply and output current vs temperature ambient temperature ( c) C 50 C 25 0 25 50 75 100 125 supply current (2ma) output current (50ma/div) quiescent supply current sinking output current sourcing output current
opa692 10 sbos236c www.ti.com typical characteristics: v s = 5v (cont.) t a = +25 c, g = +2, and r l = 100 ? (see figure 1 for dc performance only), unless otherwise noted. 2 1.5 1 0.5 0 C 0.5 C 1 C 1.5 C 2 typical dc drift over temperature ambient temperature ( c) C 50 C 25 0 25 50 75 100 125 input offset voltage (mv) 40 30 20 10 0 C 10 C 20 C 30 C 40 input bias currents ( a) input offset voltage noninverting input bias current inverting input bias current 5 4 3 2 1 0 C 1 C 2 C 3 C 4 C 5 output voltage and current limitations i o (ma) C 300 C 250 C 200 C 150 C 100 C 50 0 50 100 150 200 250 300 v o (v) 100 ? load line 50 ? load line 25 ? load line output current limited 1w internal power limit 1w internal power limit output current limit large-signal disable/enable response output voltage (400mv/div) time (200ns/div) 2.0 1.6 1.2 0.8 0.4 0 v dis (2v/div) 6.0 4.0 2.0 0 output voltage v dis v in = +1v disable/enable glitch output voltage (10mv/div) time (20ns/div) 30 20 10 0 C 10 C 20 v dis (2v/div) 6.0 4.0 2.0 0 output voltage (0v input) v dis 10 1 0.1 closed-loop output impedance frequency (hz) 10k 100m 100k 1m 10m output impedance ( ? ) opa692 402 ? +5v C 5v 402 ? 50 ? z o
opa692 11 sbos236c www.ti.com typical characteristics: v s = +5v t a = +25 c, g = +2, and r l = 100 ? (see figure 2 for ac performance only), unless otherwise noted. 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 small-signal pulse response time (5ns/div) output voltage (100mv/div) g = +2 v o = 0.5vp-p 4.1 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 large-signal pulse response time (5ns/div) output voltage (400mv/div) g = +2 v o = 2vp-p 70 60 50 40 30 20 10 0 capacitive load (pf) 1 10 100 1k recommended r s vs capacitive load r s ( ? ) 1 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 frequency (hz) 0 500m 250m small-signal frequency response normalized gain (1db/div) g = +1 g = +2 g = C 1 7 6 5 4 3 2 1 0 frequency (hz) 0 250m 125m large-signal frequency response gain (1db/div) r l = 100 ? to 2.5v v o = 0.5vp-p v o = 2vp-p v o = 1vp-p 9 6 3 0 C 3 C 6 C 9 frequency response vs capacitive load frequency (25mhz/div) 0 250mhz 125mhz normalized gain to capacitive load (db) opa692 402 ? 402 ? 57.6 ? 806 ? 806 ? 1k ? v in +5v v o r s (1k ? is optional) c l 0.1 f 0.1 f c l = 10pf c l = 22pf c l = 47pf c l = 100pf
opa692 12 sbos236c www.ti.com typical characteristics: v s = +5v (cont.) t a = +25 c, g = +2, and r l = 100 ? (see figure 2 for ac performance only), unless otherwise noted. harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 harmonic distortion (dbc) C 50 C 60 C 70 C 80 C 90 v o = 2vp-p r l = 100 ? to 2.5v 2nd-harmonic 3rd-harmonic C 30 C 35 C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 single-tone load power (dbm) C 14 C 12 C 10 C 8 C 6 C 4 C 20 2 2-tone, 3rd-order intermodulation spurious 3rd-order spurious level (dbc) dbc = db below carriers load power at matched 50 ? load 50mhz 20mhz 10mhz harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 2 3 harmonic distortion (dbc) C 60 C 65 C 70 C 75 C 80 r l = 100 ? to 2.5v f = 5mhz 2nd-harmonic 3rd-harmonic C 60 C 65 C 70 C 75 C 80 load resistance ( ? ) 100 1k harmonic distortion vs load resistance harmonic distortion (dbc) 2nd-harmonic 3rd-harmonic v o = 2vp-p f = 5mhz
opa692 13 sbos236c www.ti.com applications information wideband buffer operation the opa692 gives the exceptional ac performance of a wideband current-feedback op amp with a highly linear, high- power output stage. it features internal r f and r g resistors that make it easy to select a gain of +2, +1, or C 1 without any external resistors. requiring only 5.1ma quiescent current, the opa692 will swing to within 1v of either supply rail and deliver in excess of 160ma at room temperature. this low output headroom requirement, along with supply voltage indepen- dent biasing, gives remarkable single (+5v) supply operation. the opa692 will deliver greater than 200mhz bandwidth driving a 2vp-p output into 100 ? on a single +5v supply. previous boosted output stage amplifiers have typically suf- fered from very poor crossover distortion as the output current goes through zero. the opa692 achieves a comparable power gain with much better linearity. the primary advantage of a current-feedback op amp over a voltage-feedback op amp is that ac performance (bandwidth and distortion) is relatively independent of signal gain. figure 1 shows the dc-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the 5v electrical and typical characteristics. for test purposes, the input imped- ance is set to 50 ? with a resistor to ground and the output impedance is set to 50 ? with a series output resistor. voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dbm) are defined at a matched 50 ? load. for the circuit of figure 1, the total effective load will be 100 ? || 804 ? = 89 ? . the disable control line ( dis ) is typically left open to ensure normal amplifier operation. in addition to the usual power-supply decoupling capacitors to ground, a 0.1 f capacitor can be included between the two power-supply pins. this optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3db to 6db. figure 2 shows the ac-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5v electrical and typical characteristics. though not a rail-to-rail design, the opa692 requires minimal input and output voltage head- room compared to other very wideband current-feedback op amps. it will deliver a 3vp-p output swing on a single +5v supply with greater than 150mhz bandwidth. the key re- quirement of broadband single-supply operation is to main- tain input and output signal swings within the usable voltage ranges at both the input and the output. the circuit of figure 2 establishes an input midpoint bias using a simple resistive divider from the +5v supply (two 806 ? resistors). the input signal is then ac-coupled into this midpoint voltage bias. the input voltage can swing to within 1.5v of either supply pin, giving a 2vp-p input signal range centered between the supply pins. the input impedance matching resistor (57.6 ? ) used for testing is adjusted to give a 50 ? input match when the parallel combination of the biasing divider network is included. the gain resistor (r g ) is ac-coupled, giving the circuit a dc gain of +1 which puts the input dc bias voltage (2.5v) on the output as well. again, on a single +5v supply, the output voltage can swing to within 1v of either supply pin while delivering more than 120ma output current. a demand- ing 100 ? load to a midpoint bias is used in this characteriza- tion circuit. the new output stage used in the opa692 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5v supply, 3rd-harmonic distortion typical characteristics. figure 1. dc-coupled, g = +2, bipolar supply, specifica- tion and test circuit. figure 2. ac-coupled, g = +2, single-supply specification and test circuit. opa692 +5v C 5v 50 ? load 50 ? 50 ? 50 ? source r g 402 ? r f 402 ? + 6.8 f 0.1 f + 6.8 f 0.1 f dis v in single-supply adc interface most modern, high-performance adcs (such as the texas instruments ads8xx and ads9xx series) operate on a single +5v (or lower) power supply. it has been a considerable challenge for single-supply op amps to deliver a low-distor- tion input signal at the adc input for signal frequencies opa692 +5v +v s dis v s /2 806 ? 100 ? v o v in 806 ? r g 402 ? r f 402 ? 0.1 f 0.1 f + 6.8 f 0.1 f 50 ? source 57.6 ?
opa692 14 sbos236c www.ti.com exceeding 5mhz. the high slew rate, exceptional output swing, and high linearity of the opa692 make it an ideal single-supply adc driver. figure 3 shows an example input interface to a very high performance 10-bit, 60msps cmos converter. the opa692 in the circuit of figure 3 provides 190mhz bandwidth operating at a signal gain of +2 with a 2vp-p output swing. the noninverting input bias voltage is referenced to the midpoint of the adc signal range by dividing off the top and bottom of the internal adc reference ladder. with the gain resistor (r g ) ac-coupled, this bias voltage has a gain of +1 to the output, centering the output voltage swing as well. tested performance at a 20mhz analog input frequency and a 60msps clock rate on the converter gives > 58dbc sfdr. wideband video multiplexing one common application for video speed amplifiers that include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. this simple wired-or video multiplexer can be easily implemented using the opa692, as shown in figure 4. figure 3. wideband, ac-coupled, single-supply adc driver. figure 4. 2-channel video multiplexer. opa692 402 ? +2.5v dc bias ads826 10-bit 60msps 50 ? 2vp-p dis 22pf input 402 ? refb reft cm input 0.1 f 0.1 f 1vp-p 2k ? 0.1 f +3.5v 2k ? 0.1 f +1.5v +5v clock +5v r g r f opa692 2k ? v out 75 ? cable rg-59 68.1 ? 68.1 ? 75 ? 402 ? 402 ? video 1 +5v +5v | v out | < 2.6v C 5v opa692 2k ? 75 ? 402 ? 402 ? video 2 C 5v +5v v dis dis dis
opa692 15 sbos236c www.ti.com typically, channel switching is performed either on sync or retrace time in the video signal. the two inputs are approxi- mately equal at this time. the make-before-break disable characteristic of the opa692 ensures that there is always one amplifier controlling the line when using a wired-or circuit (see figure 4). since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resis- tors (68.1 ? in this case). when one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. the matching resistors have been set to get a signal gain of +1 at the load while providing > 20db return loss at the load. the video multiplexer connection (see figure 4) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated 1.2v maximum for standard video signal levels. in any case, v out must be < 2.6vp-p in order to not exceed the absolute maximum differential input voltage ( 1.2v) on the disabled channel. the disable operation section shows the turn-on and turn-off switching glitches using a grounded input for a single chan- nel is typically less than 50mv. where two outputs are switched (see figure 4), the output line is always under the control of one amplifier or the other due to the make-before- break disable timing. in this case, the switching glitches for two 0v inputs drops to < 20mv. 4-channel frequency channelizer the circuit of figure 5 is a 4-channel multiplexer. in this circuit the opa691 provides the drive for all four channels. each channel includes a bandpass filter and each bandpass filter is set for a different frequency band. this allows the channelizing part of this circuit. the role of the opa692 is to provide impedance isolation. this is done through the use of four matching resistances (59 ? in this case). these match- ing resistors ensure that the signals will combine during the transition between channels. they have been used to get a gain of +1 at the load. this circuit may be used with a different number of channels. its limitation comes from the drive requirement for each channel, as well as the minimum acceptable return loss. the output resistor value (r o ) to keep a gain of +1 at the load, depends on the number of channels. for the opa692, equation 1 gives: (1) r n n o = ? ( ) + [] ?+ ?? ( ) + [] ? ? ? ? ? ? ? ? 75 2 804 2 1 241200 75 2 804 1 2 ?? ? ?? C C where n = number of devices in multiplexer. opa692 v out 75 ? cable 75 ? load rg-59 75 ? opa691 75 ? r o 59 ? r o 59 ? r o 59 ? r o 59 ? #1 dis 1 opa692 75 ? 75 ? #2 dis 2 opa692 75 ? 75 ? #3 dis 3 +5v C 5v +5v C 5v +5v C 5v +5v C 5v +5v C 5v g = +2 stages opa692 75 ? 75 ? #4 dis 4 figure 5. 4-channel frequency channelizer.
opa692 16 sbos236c www.ti.com delay-equalized low-pass filter the circuit in figure 6 realizes a 5th-order butterworth low- pass filter with a C 3db bandwidth of 20mhz and group delay equalization. this filter is based on the krc active filter topology using amplifiers with a fixed positive gain 1. the opa692 makes a good amplifier for this type of filter. the first stage is the group delay equalizer, which is based on a gain of C 1. the second stage has a high-q pole, uses a gain of +2 for minimum component sensitivity, and also produces a real pole. the last stage has a low-q pole, and uses a gain of +1 for minimum component sensitivity. the component values have been predistorted to compensate for the op amps parasitic effects. the low-q pole section was placed last to minimize noise peaking in the passband, while maintaining good dynamic range performance. precision voltage buffer the precision buffer in figure 7 combines the dc precision and low 1/f noise of the opa227 with the high-speed perfor- mance of the opa692. the 80.6k ? resistor makes the high- frequency and low-frequency nominal gains equal. the opa692 takes over from the opa227 at approximately 32khz. opa692 115 ? 402 ? 49.9 ? 105 ? 226 ? 402 ? 100pf 220pf 56pf 27pf v in v out opa692 402 ? 402 ? 95.3 ? 226 ? 68pf 39pf opa692 402 ? 402 ? (open) figure 7. precision wideband, unity-gain buffer. opa227 opa692 402 ? 402 ? 80.6k ? 200 ? v in v out C 5v +5v 200 ? 2.7nf 2.7nf figure 6. butterworth lp filter with delay equalization. design-in tools demonstration boards two pc boards are available to assist in the initial evaluation of circuit performance using the opa692 in its two package styles. all of these are available free as an unpopulated pc
opa692 17 sbos236c www.ti.com board delivered with descriptive documentation. the sum- mary information for these boards is shown in the table below. over-temperature specifications because the output stage junction temperatures are higher than the minimum specified operating ambient. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an adc including additional external capacitance which may be recommended to improve adc linearity. a high-speed amplifier like the opa692 can be very susceptible to decreased stability and frequency re- sponse peaking when a capacitive load is placed directly on the output pin. when the amplifier s open-loop output resis- tance is considered, this capacitive load introduces an addi- tional pole in the signal path that can decrease the phase margin. several external solutions to this problem have been suggested. when the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capaci- tive load. this does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. the additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. the typical characteristics show the recommended r s vs capacitive load and the resulting frequency response at the load. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa692. long pc board traces, unmatched cables, and connections to multiple de- vices can easily cause this value to be exceeded. always consider this effect carefully, and add the recommended series resistor as close as possible to the opa692 output pin (see the board layout guidelines section). distortion performance the opa692 provides good distortion performance into a 100 ? load on 5v supplies. relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5v supply. generally, until the funda- mental signal reaches very high-frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rd- harmonic component. focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network in the noninverting configuration (see figure 1) this is the sum of r f + r g , while in the inverting configuration, it is just r f . also, providing an additional supply decoupling capacitor (0.1 f) between the supply pins (for bipolar operation) im- proves the 2nd-order distortion slightly (3db to 6db). in most op amps, increasing the output voltage swing increases harmonic distortion directly. the typical characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate while the 3rd-harmonic increases at a much lower rate than the expected 3x. where the test power doubles, the difference between it and the 2nd-harmonic decreases less than the board literature part request product package number number OPA692ID so-8 dem-opa68xu sbou009 OPA692IDbv sot23-6 dem-opa6xxn sbou010 to request any of these boards, check the texas instruments web site at www.ti.com. operating suggestions gain setting setting the gain with the opa692 is very easy. for a gain of +2, ground the C in pin and drive the +in pin with the signal. for a gain of +1, leave the C in pin open and drive the +in pin with the signal. for a gain of C 1, ground the +in pin and drive the C in pin with the signal. as the internal resistor values (not their ratio) change over temperature and process, external resistors should not be used to modify the gain. output current and voltage the opa692 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic op amp. under no-load conditions at +25 c, the output voltage typically swings closer than 1v to either supply rail; the tested swing limit is within 1.2v of either rail. into a 15 ? load (the minimum tested load), it is specified to deliver more than 160ma. the specifications described previously, though familiar in the industry, consider voltage and current limits separately. in many applications, it is the voltage times current, or v-i product, which is more relevant to circuit operation. refer to the output voltage and current limitations plot in the typical characteristics. the x- and y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. the four quadrants give a more detailed view of the opa692 output drive capabilities, noting that the graph is bounded by a safe operating area of 1w maximum internal power dissipation. superimposing resistor load lines onto the plot shows that the opa692 can drive 2.5v into 25 ? , or 3.5v into 50 ? without exceeding the output capabilities or the 1w dissipation limit. a 100 ? load line (the standard test circuit load) shows the full 3.9v output swing capability (see the electrical characteristics). the minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. only at cold startup will the output current and voltage decrease to the numbers shown in the electrical characteristics. as the output transistors deliver power, their junction temperatures increase, decreasing their v be s (increasing the available output voltage swing), and increasing their current gains (increasing the available output current). in steady-state operation, the available output volt- age and current is always greater than that shown in the
opa692 18 sbos236c www.ti.com figure 8. noise model. expected 6db, while the difference between it and the 3rd decreases by less than the expected 12db. this also shows up in the 2-tone, 3rd-order intermodulation spurious (im3) response curves. the 3rd-order spurious levels are extremely low at low output power levels. the output stage continues to hold them low even as the fundamental power reaches very high levels. as the typical characteristics show, the spurious intermodulation pow- ers do not increase as predicted by a traditional intercept model. as the fundamental power level increases, the dynamic range does not decrease significantly. for two tones centered at 20mhz, with 10dbm/tone into a matched 50 ? load (i.e., 2vp-p for each tone at the load, which requires 8vp-p for the overall 2-tone envelope at the output pin), the typical characteristics show 58dbc difference between the test-tone power and the 3rd- order intermodulation spurious levels. this exceptional perfor- mance improves further when operating at lower frequencies. noise performance the opa692 offers an excellent balance between voltage and current noise terms to achieve low output noise. the inverting current noise (15pa/ hz ) is significantly lower than earlier solutions while the input voltage noise (1.7nv hz ) is lower than most unity-gain stable, wideband, voltage-feedback op amps. this low input voltage noise was achieved at the price of higher noninverting input current noise (12pa/ hz ). as long as the ac source impedance looking out of the noninverting node is less than 100 ? , this current noise will not contribute significantly to the total output noise. the op amp input voltage noise and the two input current noise terms combine to give low output noise for the gain settings, available using the opa692. figure 8 shows the op amp noise analysis model with all the noise terms included. in this model, all noise terms are taken to be noise voltage or current density terms in either nv/ hz or pa/ hz . the total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. equation 2 shows the general form for the output noise voltage using the terms shown in figure 8. (2) e e i r ktr ng i r ktr ng o ni bn ss bi f f =+ ( ) + ? ? ? ? + ( ) + 2 2 2 2 44 dividing this expression by the noise gain (ng = (1 + r f /r g )) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in equation 3. (3) e e i r ktr ir ng ktr ng nnibn ss bi f f =+ ( ) ++ ? ? ? ? ? ? + 2 2 2 4 4 evaluating these two equations for the opa692 circuit and component values (see figure 1) will give a total output spot noise voltage of 8.2nv/ hz and a total equivalent input spot noise voltage of 4.1nv/ hz . this total input-referred spot noise voltage is higher than the 1.7nv/ hz specification for the op amp voltage noise alone. this reflects the noise added to the output by the inverting current noise times the feed- back resistor. dc accuracy the opa692 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate dc accuracy. the electrical characteristics show an input offset voltage com- parable to high-speed voltage-feedback amplifiers. however, the two input bias currents are somewhat higher and are unmatched. bias current cancellation techniques will not reduce the output dc offset for opa692. as the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. evaluating the configuration of figure 1, using worst-case +25 c input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: (ng ? v os (max)) + (i bn ? r s /2 ? ng) (i bi ? r f ) where ng = noninverting signal gain = (2 ? 2.5mv) + (35 a ? 25 ? ? 2) (402 ? ? 25 a) = 5mv + 1.75mv 10.05mv = C 13.3mv +16.80mv minimizing the resistance seen by the noninverting input will give the best dc offset performance. for significantly improved dc accuracy, consider the preci- sion buffer circuit (see figure 7). disable operation the opa692 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. if the dis control pin is left unconnected, the opa692 will operate normally. to disable, 4kt r g r g r f r s opa692 i bi e o i bn 4kt = 1.6e C 20j at 290 k e rs e ni 4ktr s 4ktr f
opa692 19 sbos236c www.ti.com the control pin must be asserted low. figure 9 shows a simplified internal circuit for the disable control feature. in normal operation, base current to q1 is provided through thermal analysis due to the high output power capability of the opa692, heatsinking or forced airflow may be required under extreme operating conditions. maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d ? ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). under this condition p dl = v s 2 /(4 ? r l ), where r l includes feedback network loading. note that it is the power in the output stage and not in the load that determines internal power dissipation. as a worst-case example, compute the maximum t j using an OPA692IDbv (sot23-6 package) in the circuit of figure 1 operating at the maximum specified ambient temperature of +85 c and driving a grounded 20 ? load to +2.5v dc : p d = 10v ? 5.8ma + 5 2 /(4 ? (20 ? || 800 ? )) = 378mw maximum t j = +85 c + (0.39w ? 150 c/w) = 142 c although this is still well below the specified maximum junction temperature, system reliability considerations may require lower junction temperatures. remember, this is a worst-case internal power dissipation use your actual sig- nal and load to compute p dl . the highest possible internal dissipation occurs if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. this puts a high current through a large internal voltage drop in the output transistors. the output voltage and current limitations plot shown in the typical characteristics include a boundary for 1w maximum internal power dissipation under these condi- tions. board layout guidelines achieving optimum performance with a high-frequency am- plifier like the opa692 requires careful attention to board layout parasitics and external component types. recommen- dations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output pin can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted capacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbroken elsewhere on the board. the 110k ? resistor while the emitter current through the 15k ? resistor sets up a voltage drop that is inadequate to turn on the two diodes in q1 s emitter. as v dis is pulled low, additional current is pulled through the 15k ? resistor eventu- ally turning on these two diodes ( 75 a). at this point, any further current pulled out of v dis goes through those diodes holding the emitter-base voltage of q1 at approximately 0v. this shuts off the collector current out of q1, turning the amplifier off. the supply current in the disable mode is only that required to operate the circuit of figure 8. additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). when disabled, the output and input nodes go to a high- impedance state. if the opa692 is operating in a gain of +1, this will show a very high impedance (4pf || 1m ? ) at the output and exceptional signal isolation. if operating at a gain of +2, the total feedback network resistance (r f + r g ) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. if configured at a gain of C 1, the input and output will be connected through the feedback network resistance (r f + r g ) giving relatively poor input to output isolation. one key parameter in disable operation is the output glitch when switching in and out of the disabled mode. the typical characteristics show these glitches for the circuit of figure 1 with the input signal set to 0v. the glitch waveform at the output pin is plotted along with the dis pin voltage. the transition edge rate (dv/dt) of the dis control line will influence this glitch. slowing this edge can be achieved by adding a simple rc filter into the v dis pin from a higher speed logic line. if extremely fast transition logic is used, a 2k ? series resistor between the logic gate and the dis input pin will provide adequate bandlimiting using just the parasitic input capacitance on the dis pin while still ensuring an adequate logic level swing. 25k ? 110k ? 15k ? i s control C v s +v s v dis q1 figure 9. simplified disable control circuit.
opa692 20 sbos236c www.ti.com external pin +v cc C v cc internal circuitry b) minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1 f decoupling capacitors. at the device pins, the ground and power-plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. the power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. an optional supply decoupling capaci- tor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. larger (2.2 f to 6.8 f) decoupling capacitors, effective at lower frequen- cies, should also be used on the main supply pins. these may be placed somewhat further from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external compo- nents will preserve the high-frequency performance of the opa692. any external resistors should be a very low reactance type. surface-mount resistors work best and allow a tighter overall layout. metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. again, keep their leads and pc-board trace length as short as possible. never use wirewound type resistors in a high-frequency application. all external compo- nents should also be placed close to the package. d) connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the plot of recommended r s vs capacitive load. low parasitic capacitive loads (< 5pf) may not need an r s because the opa692 is nominally compensated to operate with a 2pf parasitic load. if a long trace is required, and the 6db signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance trans- mission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 ? environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion vs load plots. with a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the opa692 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating im- pedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace imped- ance. the high output voltage and current capability of the opa692 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. if the 6db attenuation of a doubly-termi- nated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of r s vs capacitive load. this will not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high-speed part like the opa692 is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket can create an ex- tremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa692 onto the board. input and esd protection the opa692 is built using a very high-speed complementary bipolar process. the internal junction breakdown voltages are relatively low for these very small geometry devices. these breakdowns are reflected in the absolute maximum ratings table. all device pins have limited esd protection using internal diodes to the power supplies, as shown in figure 10. figure 10. internal esd protection. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa692), current-limiting series resistors should be added into the two inputs. keep these resistor values as low as possible since high values degrade both noise performance and frequency response.
opa692 21 sbos236c www.ti.com package drawings d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 C 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
opa692 22 sbos236c www.ti.com package drawings (cont.) dbv (r-pdso-g6) plastic small-outline 0,10 m 0,20 0,95 0 C 8 0,25 0,55 0,35 gage plane 0,15 nom 4073253-5/g 01/02 2,60 3,00 0,50 0,25 1,50 1,70 4 6 3 1 2,80 3,00 1,45 0,95 0,05 min seating plane 6x notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) OPA692ID active soic d 8 100 none cu nipdau level-3-240c-168 hr OPA692IDbvr active sot-23 dbv 6 3000 none cu nipdau level-3-235c-168 hr OPA692IDbvt active sot-23 dbv 6 250 none cu nipdau level-3-235c-168 hr OPA692IDr active soic d 8 2500 none cu nipdau level-3-240c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 1-feb-2005 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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